- Evaluate performance & ease of use of measurement solutions for interface board application.
- Increase wafer sort quality on basis of scan & enhanced IDDQ tests.
- Reduce overall test costs.
- Pave the way for high quality tests using a low-cost DFT test platform.
- IDDQ Fault coverage >= 95%. Motorola LB detail.
- Module and Test platform
Module and Test platform
- QD-1000 on QI-0003 support module.
- Verigy 83K & 93K test systems.
- Motorola DFT Chip
- Motorola Product
- 300K gates – 8K RAM – DSP processor core – Analog circuitry
- TSMC 0.18µm CMOS
- 3 supplies – I/O, Analog, Core (IDDQ)
- 61 I/O – 84 MBGA, 4340 * 4340 µm2
- Typical leakage: 30µA
Automated Test Pattern Generation and Test Program Creation Flow:
- Add monitor black box info to circuit netlist –> Modified netlist (DUT + monitor)
- ATPG Scan & IDDQ vector generation (FastScan, IDDQ Fault coverage target: > 95%)
- Add monitor configuration routine at the start of the test program
- Insert monitor timing at IDDQ strobe points identified by the ATPG tool
- Generation of tester specific file (convert WGL to ATE specific format)
Making use of the QI-0003 monitor product, with a typical measurement time of 100µs per measurement, allowed to drastically increase the number of Iddq vectors used whilst considerably reducing the total IDDQ test time, thereby reducing test costs and gaining in product quality. The results obtained further pave the pathway for running a high quality Scan+IDDQ based test approach on low cost DFT platform.
- number of Iddq vectors: increased from 40 to 911 (23x increase)
- Total Iddq test time: reduced from 1.2s to 0.315s (4x reduction)
- Measurement time: reduced from 30ms to 150µs/vector (200x reduction)
- Overall gain factor : ~92
- Savings (test time only): 60k$/Mdev,
- plus (not quantified) reduced die cost, reduced packaging cost, reduced FA costs, less field returns,…
- Improved product quality
Making use of Q-Star Tests high quality and high speed interface board add-on solutions allows Motorola to increase the number of IDDQ vectors used and meanwhile to simplify its test process, cut on test time, reduce product costs and in addition to improve its product quality.
Manhaeve H., Vaccaro J, Benecke L., A Real World Application Used to Implement a True IDDQ based Test Strategy. Proceedings of the IEEE International Workshop on Current and Defect Based Testing DBT2002, pp. 53-60, 28 April 2002, Monterey, California.
Manhaeve H., Vaccaro J, Benecke L, Prystasz D., A Real World Application Used to Implement a True IDDQ based Test Strategy (Facts and Figures). Proceedings of the 7th IEEE European Test Workshop ETW02, pp. 81-86, 26-29 May 2002, Corfu, Greece.
Manhaeve H., True IDDQ Test and its Real-life Application, Proceedings of the 9th Annual International KGD Packaging and Test Workshop, (on CDROM), September 2002, Napa, California